Circuit design of a dual-versioning L1 data cache

The Skewed Distribution of Working Sets: Leveraging Randomness for Cache Design

The increasing gap between processor and memory speeds, as well as the introduction of multicore CPUs, have exacerbated the dependency of CPU performance on the memory subsystem. This trend motivates the search for more efficient caching mechanisms, enabling both faster service of frequently used blocks and decreased power consumption. This thesis explores the temporal locality phenomenon in an...

L1 Cache Decomposition for Energy Efficient Processors

The L1 data cache is a time-critical module and, at the same time, a major source of energy consumption. To reduce its energy-delay product, we apply two principles of low power design: specialize part of the cache structure and break down the cache into smaller caches. To this end, we propose a L1 cache that combines new designs of a stack cache and a PSA cache. Individually, our stack and PSA...

Two-level Data Prefetching

Data prefetching has been shown to be an effective tool in hiding part of the latency associated with cache misses in modern processors. Traditionally, data prefetchers fetch data into a small prefetch buffer near the L1 for low latency, or the L2 cache for greater coverage and less cache pollution. However, with the L1–L2 cache speed gap growing, significant performance gains can be obtained i...

A Power Aware Cache and Register File Design Space Exploration

A 400-MHz S/390 Microprocessor - Solid-State Circuits, IEEE Journal of

A microprocessor implementing IBM S/390 architecture operates in a 10 + 2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2m Le CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm 17.30 mm with about 7.8 million transistors. The power supply is 2.5 V and measured power dissipation at 300 MHz is 37 W. The microproc...